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CXP87300
CMOS 8-bit Single Chip Microcomputer
Description The CXP87300 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP87352/87360.
Piggyback/ evaluator type
100 pin PQFP (Ceramic)
Features * A wide instruction set (213 instructions) which cover various types of data. LQFP supported QFP supported -- 16-bit operation/multiplication and division/ boolean bit operation instructions * Minimum instruction cycle 333ns at 12MHz operation (3.0 to 5.5V) 250ns at 16MHz operation (4.5 to 5.5V) 122s at 32kHz operation * Applicable EPROM LCC type 27C256, LCC type 27C512 (Maximum 60Kbytes are available.) * Incorporated RAM capacity 2048 bytes * Peripheral functions - A/D converter 8-bit, 12-channel, successive approximation method (Conversion time of 20s/16MHz) - Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel - Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32kHz timer/counter - High precision timing pattern generator PPG 19-pin, 32-stage programmable RTG 5 pins, 2 channels - PWM/DA gate output PWM output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output 13 bits, 4channels - Servo input control Capstan FG, drum FG/PG, CTL input - VSYNC separator - FRC capture unit Incorporated 26-bit and 8-stage FIFO - PWM output 14 bits, 1 channel - VISS/VASS circuit Pulse duty auto detection circuit - Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO - General purpose prescaler 7 bits (SYNC1 input frequency division, FRC capture possible.) - HSYNC counter 12-bit event counter (SYNC1 input count) * Interruption 22 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP87300. Refer to the Products List for details. Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94X15A68-PS
CXP87300
Pin Assignment in Piggyback Mode (QFP package)
PI3/TO/DDO/ADJ
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
VDD
NC
Vss
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 80 79 78 77 76 75 74 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVss PF4/AN8
A12
A15
A14
VDD
A13
TX
TEX
PI1/RMC
PI2/PWM
PI5/SCK1
73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
9 10 11 12 13 14 15 16 17 18 19 20 21 4 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6
23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND
NC
D1
D2
D3
D4
D5
22
A7
8
NC
Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND.
-2-
PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
Vss
MP
SI0
CXP87300
Pin Assignment in Piggyback Mode (LQFP package)
PI3/TO/DDO/ADJ
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
PI1/RMC
PI2/PWM
PI5/SCK1
PI6/SO1
Vss
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TX
TEX
NC
VDD
PI7/SI1
PE0/INT0/CKOUT
PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND.
-3-
PF7/AN11
PF6/AN10
PF5/AN9
PF4/AN8
EXTAL
SCK0
XTAL
AVss
RST
SO0
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
Vss
MP
SI0
CXP87300
Pin Assignment in Evaluator Mode (QFP package)
PI3/TO/DDO/ADJ
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
Vss
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 80 79 78 77 76 75 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVss PF4/AN8
TX
TEX
VDD
PI1/RMC
PI2/PWM
PI5/SCK1
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A7/D7
7 8 9 10
A12
A15
4 11 12 13 14 15 16 17 18 19 20 21 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13
3
2
NC
1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON
14 15 16 17 18 19 20
23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SYNC
GND
RST
WR
NC
C2
C1
22
A14
VDD
A13
Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND.
-4-
PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
Vss
MP
SI0
CXP87300
Pin Assignment in Evaluator Mode (LQFP package)
PI3/TO/DDO/ADJ
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
PI1/RMC
PI2/PWM
PI5/SCK1
PI6/SO1
Vss
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 A15 A12 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 RD WR SYNC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 HALT A10 E/P I/T MON RST C1 C2 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TX
TEX
VDD
PI7/SI1
PE0/INT0/CKOUT
PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND.
-5-
PF7/AN11
PF6/AN10
PF5/AN9
PF4/AN8
EXTAL
SCK0
XTAL
AVss
RST
SO0
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
Vss
MP
SI0
CXP87300
EPROM Read Timing (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Item Address data input delay time Address data hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 1001 752 Unit ns ns
tACC tIH
1 At 12MHz operation (VDD = 4.5 to 5.5V) 2 At 12MHz operation (VDD = 3.0 to 5.5V), At 16MHz operation (VDD = 4.5 to 5.5V)
0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD
Products List Products Option item Mask product CXP87352 Package ROM capacity Pull-up resistor for reset pin Input circuit format1 CXP87360 Piggyback/evaluator product CXP87300-U01Q CXP87300-U01R CXP87300-U02Q CXP87300-U02R 100-pin ceramic PQFP EPROM 60Kbytes 27C512 x 1 27C512 x 1 Existent TTL schmitt CMOS schmitt CMOS schmitt 27C256 x 2 CXP87300-U05R
100-pin plastic QFP/LQFP 52Kbytes 60Kbytes
Existent/Non-existent CMOS schmitt/TTL schmitt
1 On PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.
-6-
CXP87300
Piggyback mode/evaluator mode can be switched as shown below.
Evaluator mode
Pin 1 marking
Piggyback mode
Piggyback/evaluator product
LCC type EPROM Pin 1 marking
Pin 1 index
Note) CPU probe
(27C512 only)
EPROM adaptor Pin 1 marking
Note) Evaluation cap should be connected to CPU probe.
Pin 1 index
U01R and U02R used
CPU probe for LQFP
LCC type EPROM for low voltage Pin 1 marking
EPROM adaptor Pin 1 marking
U05R used
Address Lower For lower address For upper address Upper
Memory space 1000H to 7FFFH 8000H to FFFFH
EPROM (27C256) 1000H to 7FFFH 0000H to 7FFFH
(27C256 only) Lower address Upper address
-7-
CXP87300
Package Outline
Unit: mm
100PIN PQFP (CERAMIC)
PIN NO. 1 INDEX INDEX 100
18.7 16.3 0.2 81 81 100 PIN No. 1 INDEX
1
80
80
1 0.65 0.05
4.5 1.27 0.13
22.3 0.25
18.12 0.2
12.02
14.22
24.7
6.0
0.3
1.0
0.7
30
51
51
30
31 9.48 11.66 15.58 0.2
50
1.3 0.3
50 0.45
31
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g
3.57 0.36
JEDEC CODE
+ 0.05 0.15 - 0.02
0.50 0.25
100PIN PQFP (CERAMIC)
16.0 0.4 14.0 0.2 75 76 0.5 0.05 51 12.4
50 0.5 0.05 3.2 0.2 1.5 0.8 0.2 26
10.44 MAX
0.3 0.08 + 0.08 0.18 - 0.03 INDEX
12.0 0.15
+ 0.08 0.18 - 0.03
100 1 INDEX 12.8 0.2 25
PACKAGE STRUCTURE
PACKAGE MATERIAL CERAMIC GOLD PLATING 42 ALLOY 2.2g
+ 0.05 0.127 - 0.02
+ 0.15 0.2 - 0.13
6.9
SONY CODE EIAJ CODE JEDEC CODE
PQFP-100C-L02 AQFP100-C-1414-A
LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
3.32
-8-
12.0 0.15

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